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U2109I·SUNDAY WORKSHOP: MIPSfpga: Hands-on Learning using an Unobfuscated Commercial MIPS Core
Workshop · Sponsored Sessions
Sun. June 24, 2018 9:00 AM to 12:00 PM
Room 355 A, Convention Center - Salt Palace
Session Description

Free ticketed event
This MIPSfpga workshop shows how to access and use the MIPSfpga package, which includes the Verilog source code of the commercial MIPS microAptiv processor, all required development tools for MIPSfpga, a comprehensive Getting Started Guide that describes, among other things, the MIPSfpga system and how to simulate and run MIPSfpga on different FPGAs, and 25 hands-on labs. These labs guide users in writing, debugging, and running programs on the MIPSfpga core; extending the core to interface with I/O (i.e., audio, sensors, LCDs); using interrupts and performance counters; exploring and modifying the pipeline and hazard logic; adding new instructions manually and using CorExtend; and exploring and modifying the memory system, including the caches.

The workshop shows how to use MIPSfpga to easily transition from theory to practice when teaching computer architecture, system-on-chip, and digital design principles. Attendees will learn about the MIPSfpga system, see an overview of all of the labs, and experiment with a subset of the labs on their own laptops. By the end of the workshop, attendees will have the tools, resources, and experience to use MIPSfpga to increase hands-on learning and understanding of computer architecture, system-on-chip design, hardware-software co-design, embedded systems, and memory system design.

Speakers
  1. Prof. Sarah L Harris

    Dr. Sarah L. Harris is an Associate Professor at the University of Nevada, Las Vegas (UNLV). She earned her M.S. and Ph.D. from Stanford University and was an Assistant and Associate Professor at Harvey Mudd College for 10 years before joining the UNLV faculty. Dr. Harris has worked at companies including Hewlett Packard and NVIDIA. Her research interests include embedded systems, bio-inspired robotics, and hardware acceleration. She is also a co-author of the textbook Digital Design and Computer Architecture (© 2012 Morgan Kaufmann).

  2. Daniel Chaver Martinez

    University Complutense of Madrid

    Dr. Daniel Chaver Martinez is an Associate Professor at the University Complutense of Madrid (UCM). He studied Physics at the University of Santiago de Compostela (USC), Electronic Engineering at UCM, and earned his PhD at UCM in 2006. His current research includes architectural techniques for caching and for non-volatile memories and OS scheduling for asymmetric multiprocessors.

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